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參數(shù)資料
| 型號： | IBMN312164CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 128Mb(8Mbit x 4 I/O x 4 Bank) Synchronous DRAM(128M位(8M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM) |
| 中文描述： | 128Mb的（8Mbit × 4的I / O × 4行）同步DRAM（128兆位（800萬位× 4的I / O × 4組）同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 33/66頁 |
| 文件大?。?/td> | 1696K |
| 代理商： | IBMN312164CT3 |
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IBMN312164CT3
IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
06K7582.H03335A
10/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 33 of 66
Write
Recovering
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
X
L
L
L
L
H
H
H
X
L
L
L
L
H
H
H
X
L
L
L
L
H
H
H
X
L
L
H
H
L
L
H
X
L
L
H
H
L
L
H
X
L
L
H
H
L
L
H
X
L
L
H
H
L
L
H
X
L
H
L
H
L
H
H
X
L
H
L
H
L
H
H
X
L
H
L
H
L
H
H
X
L
H
L
H
L
H
H
X
OP Code
Mode Register Set
Auto or Self Refresh ILLEGAL
Precharge
Row Address Bank Activate
Column
Write
Column
Read
X
No Operation
X
Device Deselect
OP Code
Mode Register Set
X
Auto or Self Refresh ILLEGAL
X
Precharge
Row Address Bank Activate
Column
Write
Column
Read
X
No Operation
X
Device Deselect
OP Code
Mode Register Set
X
Auto or Self Refresh ILLEGAL
X
Precharge
Row Address Bank Activate
Column
Write
Column
Read
X
No Operation
X
Device Deselect
OP Code
Mode Register Set
X
Auto or Self Refresh ILLEGAL
X
Precharge
Row Address Bank Activate
Column
Write
Column
Read
X
No Operation
X
Device Deselect
ILLEGAL
X
BS
BS
BS
BS
X
X
X
X
ILLEGAL
ILLEGAL
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Row Active after t
DPL
No Operation; Row Active after t
DPL
ILLEGAL
4
4
9
9
Write
Recovering
with
Auto Pre-
charge
X
BS
BS
BS
BS
X
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Precharge after t
DPL
No Operation; Precharge after t
DPL
ILLEGAL
4
4
4, 9
4, 9
Refreshing
X
BS
BS
BS
BS
X
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after t
RC
No Operation; Idle after t
RC
ILLEGAL
Mode
Register
Accessing
X
BS
BS
BS
BS
X
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
Current State Truth Table
(Part 3 of 3)(See note 1)
Current State
Command
Action
Notes
CS
RAS CAS WE BS0,BS1
A11 - A0
Description
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-
mand is being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode
is entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t
RAS
) must be satisfied.
7. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satisfied.
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