- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379206 > IBMN312404CT3 (IBM Microeletronics) 128Mb(2Mbit x 16 I/O x 4 Bank) Synchronous DRAM(128M位(2M位 x 16 I/O x 4 組)同步動(dòng)態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | IBMN312404CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 128Mb(2Mbit x 16 I/O x 4 Bank) Synchronous DRAM(128M位(2M位 x 16 I/O x 4 組)同步動(dòng)態(tài)RAM) |
| 中文描述： | 128Mb的（2Mbit的× 16的I / O × 4行）同步DRAM（128兆位（200萬位× 16的I / O × 4組）同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 14/66頁(yè) |
| 文件大?。?/td> | 1696K |
| 代理商： | IBMN312404CT3 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)
IBMN312164CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
IBMN312804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 66
06K7582.H03335A
10/00
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. There is no CAS latency
required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same
clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subse-
quent rising clock edge until the burst length is completed. When the burst has finished, any additional data
supplied to the DQ pins will be ignored.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previ-
ous burst is interrupted, the remaining addresses are overridden by the new address and data will be written
into the device until the programmed burst length is satisfied.
Burst Write Operation
Write Interrupted by a Write
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
DQs
DIN A
0
DIN A
1
DIN A
2
DIN A
3
NOP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Extra data is masked.
The first data element and the Write
are registered on the same clock edge.
(
Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
DQs
DIN A
0
DIN B
0
DIN B
1
DIN B
2
NOP
DIN B
3
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
1 CK Interval
(Burst Length = 4, CAS latency = 2, 3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBMN312804CT3 | 128Mb(4Mbit x 8 I/O x 4 Bank) Synchronous DRAM(128M位(4M位 x 8 I/O x 4 組)同步動(dòng)態(tài)RAM) |
| IBMN312164CT3 | 128Mb(8Mbit x 4 I/O x 4 Bank) Synchronous DRAM(128M位(8M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM) |
| IBMN325404CT3 | 256Mb（4Mbit x 16 I/O x 4 Bank） Synchronous DRAM(256M位（4M位 x 16 I/O x 4 組）同步動(dòng)態(tài)RAM) |
| IBMN325804CT3 | 256Mb（8Mbit x 8 I/O x 4 Bank） Synchronous DRAM(256M位（8M位 x 8 I/O x 4 組）同步動(dòng)態(tài)RAM) |
| IBMN325164CT3 | 256Mb（16Mbit x 4 I/O x 4 Bank） Synchronous DRAM(256M位（16M位 x 4 I/O x 4 組）同步動(dòng)態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBMN364164CT3C360 | 制造商:IBM 功能描述:* |
| IBMPPC403GAJC33C1 | 制造商:IBM 功能描述: |
| IBMPPC750CLGEQ4023 | 制造商:IBM 功能描述:MPU 750CL RISC 32BIT 90NM 400MHZ 1.15V/1.8V 278FCBGA - Trays |
| IBMPPC750CLGEQ5023 | 制造商:IBM Microelectronics 功能描述:MPU 750CL RISC 32BIT 90NM 500MHZ 1.15V/1.8V 278FCBGA - Trays |
| IBMPPC750CLGEQA033 | 制造商:IBM 功能描述:MPU 750CL RISC 32BIT 90NM 1GHZ 1.15V/1.8V 278FCBGA - Trays 制造商:IBM 功能描述:IBMIBMPPC750CLGEQA033 CPU PPC 750CL 1GHZ |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。