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參數(shù)資料
| 型號： | IBMN312404CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 128Mb(2Mbit x 16 I/O x 4 Bank) Synchronous DRAM(128M位(2M位 x 16 I/O x 4 組)同步動態(tài)RAM) |
| 中文描述： | 128Mb的（2Mbit的× 16的I / O × 4行）同步DRAM（128兆位（200萬位× 16的I / O × 4組）同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 28/66頁 |
| 文件大?。?/td> | 1696K |
| 代理商： | IBMN312404CT3 |
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IBMN312164CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
IBMN312804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 28 of 66
06K7582.H03335A
10/00
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least
one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the inter-
nal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a one-
clock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends.
While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend
mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when
Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last
valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until
the Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
Clock Suspend during a Write Cycle
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
CKE
DQs
DOUT A
0
DOUT A
2
DOUT A
1
: “H” or “L”
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DOUT element at the DQs when the
suspend operation starts is held valid
(Burst Length = 4, CAS Latency = 2)
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
CKE
DQs
DIN A
2
DIN A
3
: “H” or “L”
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DIN is masked during the Clock Suspend Period
DIN A
1
DIN A
0
(Burst Length = 4, CAS Latency = 2)
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