參數(shù)資料
型號(hào): IBMN312804CT3
廠商: IBM Microeletronics
英文描述: 128Mb(4Mbit x 8 I/O x 4 Bank) Synchronous DRAM(128M位(4M位 x 8 I/O x 4 組)同步動(dòng)態(tài)RAM)
中文描述: 128Mb的(的4Mb × 8的I / O × 4行)同步DRAM(128兆位(4分位× 8的I / O × 4組)同步動(dòng)態(tài)RAM)的
文件頁數(shù): 23/66頁
文件大小: 1696K
代理商: IBMN312804CT3
IBMN312164CT3
IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
06K7582.H03335A
10/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 23 of 66
Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the
Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read
operations, valid data will continue to appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
COMMAND
READ Ax
0
NOP
NOP
NOP
NOP
NOP
*
NOP
NOP
t
CK2
,
DQs
CAS latency = 2
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT Ax
0
DOUT Ax
1
DOUT Ax
2
DOUT Ax
3
Precharge A
t
CK3
,
DQs
CAS latency = 3
DOUT Ax
0
DOUT Ax
1
DOUT Ax
2
DOUT Ax
3
t
RP
t
RP
*
Bank A can be reactivated at completion of t
.
t
is a function of clock cycle time and speed sort.
*
See the Clock Frequency and Latency table.
(Burst Length = 8, CAS Latency = 2, 3)
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PDF描述
IBMN312164CT3 128Mb(8Mbit x 4 I/O x 4 Bank) Synchronous DRAM(128M位(8M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM)
IBMN325404CT3 256Mb(4Mbit x 16 I/O x 4 Bank) Synchronous DRAM(256M位(4M位 x 16 I/O x 4 組)同步動(dòng)態(tài)RAM)
IBMN325804CT3 256Mb(8Mbit x 8 I/O x 4 Bank) Synchronous DRAM(256M位(8M位 x 8 I/O x 4 組)同步動(dòng)態(tài)RAM)
IBMN325164CT3 256Mb(16Mbit x 4 I/O x 4 Bank) Synchronous DRAM(256M位(16M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM)
IBMN612404GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM(采用雙數(shù)據(jù)速率結(jié)構(gòu)))
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