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| 型號： | IBMN325164CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb（16Mbit x 4 I/O x 4 Bank） Synchronous DRAM(256M位（16M位 x 4 I/O x 4 組）同步動態(tài)RAM) |
| 中文描述： | 256Mb的（16兆× 4的I / O × 4行）同步DRAM（256M位（1,600位× 4的I / O × 4組）同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 30/66頁 |
| 文件大?。?/td> | 1699K |
| 代理商： | IBMN325164CT3 |
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IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 30 of 66
06K0608.F39375A
10/00
Clock Enable (CKE) Truth Table
Current State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BA0,
BA1
A12 - A0
Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with No Operation
2
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
Power Down
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Power Down mode exit, all banks idle
2
L
H
L
X
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Power Down Mode
All Banks Idle
H
H
H
X
X
X
Refer to the Idle State section of the
Current State Truth Table
3
H
H
L
H
X
X
3
H
H
L
L
H
X
3
H
H
L
L
L
H
X
X
CBR Refresh
H
H
L
L
L
L
OP Code
Mode Register Set
4
H
L
H
X
X
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
L
H
X
X
3
H
L
L
L
H
X
3
H
L
L
L
L
H
X
X
Entry Self Refresh
4
H
L
L
L
L
L
OP Code
Mode Register Set
L
X
X
X
X
X
X
X
Power Down
4
Any State
other than
listed above
H
H
X
X
X
X
X
X
Refer to operations in the Current
State Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
5
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE (t
CES
) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on
the first rising clock after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more
information.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle
state.
5. Must be a legal command as defined in the Current State Truth Table.
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