參數(shù)資料
型號： IBMN325164CT3
廠商： IBM Microeletronics
英文描述： 256Mb（16Mbit x 4 I/O x 4 Bank） Synchronous DRAM(256M位（16M位 x 4 I/O x 4 組）同步動態(tài)RAM)
中文描述： 256Mb的（16兆× 4的I / O × 4行）同步DRAM（256M位（1,600位× 4的I / O × 4組）同步動態(tài)RAM）的
文件頁數(shù)： 38/66頁
文件大小： 1699K
代理商： IBMN325164CT3
IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 38 of 66
06K0608.F39375A
10/00
Clock and Clock Enable Parameters
Symbol
Parameter
-75H
-75D
-75A
-260
-360
-10
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
7.5
1000
7.5
1000
7.5
1000
7.5
1000
—
—
10
1000
10
1000
t
CK3
Clock Cycle Time, CAS Latency = 3
10
1000
10
1000
10
1000
ns
t
CK2
Clock Cycle Time, CAS Latency = 2
10
1000
15
1000
14
1000
ns
t
AC3 (A)
Clock Access Time, CAS Latency =
3
Clock Access Time, CAS Latency =
2
Clock Access Time, CAS Latency =
3
Clock Access Time, CAS Latency =
2
Clock High Pulse Width
Clock Low Pulse Width
Clock Enable Set-up Time
Clock Enable Hold Time
Power down mode Entry Time
Transition Time (Rise and Fall)
—
—
—
—
—
—
—
—
—
—
—
7
ns
1
t
AC2 (A)
—
—
—
—
—
—
—
—
—
—
—
8
ns
1
t
AC3 (B)
—
5.4
—
5.4
—
5.4
—
6
—
6
—
9
ns
2
t
AC2 (B)
—
5.4
—
—
—
—
—
6
—
9
—
9
ns
2
t
CKH
t
CKL
t
CES
t
CEH
t
SB
t
T
2.5
2.5
1.5
0.8
0
0.5
—
—
—
—
7.5
10
2.5
2.5
1.5
0.8
0
0.5
—
—
—
—
7.5
10
2.5
2.5
1.5
0.8
0
0.5
—
—
—
—
7.5
10
3
3
2
1
0
—
—
—
—
10
10
3
3
2
1
0
—
—
—
—
10
10
3
3
3
1
0
—
—
—
—
10
10
ns
ns
ns
ns
ns
ns
0.5
0.5
0.5
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
Symbol
Parameter
-75H
-75D
-75A
-260
-360
-10
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
CS
Command Setup Time
1.5
—
1.5
—
1.5
—
2
—
2
—
3
—
ns
t
CH
Command Hold Time
0.8
—
0.8
—
0.8
—
1
—
1
—
1
—
ns
t
AS
Address and Bank Select Set-up
Time
1.5
—
1.5
—
1.5
—
2
—
2
—
3
—
ns
t
AH
Address and Bank Select Hold Time
0.8
—
0.8
—
0.8
—
1
—
1
—
1
—
ns
t
RCD
RAS to CAS Delay
15
—
15
—
20
—
20
—
20
—
28
—
ns
1
t
RC
Bank Cycle Time
60
—
60
—
67.5
—
70
—
70
—
84
—
ns
1
t
RAS
Active Command Period
45
100K
45
100K
45
100K
50
100K
50
100K
56
100K
ns
1
t
RP
Precharge Time
15
—
15
—
20
—
20
—
20
—
14
—
ns
1
t
RRD
Bank to Bank Delay Time
15
—
15
—
15
—
20
—
20
—
20
—
ns
1
t
CCD
CAS to CAS Delay Time
1
—
1
—
1
—
1
—
1
—
1
—
CK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol
Parameter
-75H
-75D
-75A
-260
-360
-10
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
RSC
Mode Register Set Cycle Time
15
—
15
—
15
—
20
—
20
—
20
—
ns
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