參數(shù)資料
型號(hào)： IBMN325404CT3
廠(chǎng)商： IBM Microeletronics
英文描述： 256Mb（4Mbit x 16 I/O x 4 Bank） Synchronous DRAM(256M位（4M位 x 16 I/O x 4 組）同步動(dòng)態(tài)RAM)
中文描述： 256Mb的（的4Mb × 16的I / O × 4行）同步DRAM（256M位（4分位× 16的I / O × 4組）同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 17/66頁(yè)
文件大?。?/td> 1699K
代理商： IBMN325404CT3
IBMN325164CT3
IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
06K0608.F39375A
10/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 66
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM,
the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically
begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the
Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank
remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is
issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute
as normal with the exception that the active bank will begin to precharge before all burst read cycles have
been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last
data output. Auto-precharge can also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. How-
ever, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank.
Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write
cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has
started the bank cannot be reactivated until the Precharge time (t
RP
) has been satisfied.
When using the Auto-precharge Command, the interval between the Bank Activate Command and the begin-
ning of the internal precharge operation must satisfy t
RAS(min)
. If this interval does not satisfy t
RAS(min)
then
t
RCD
must be extended.
Burst Read with Auto-Precharge
COMMAND
NOP
NOP
NOP
NOP
Auto-Precharge
t
RP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
t
RP
*
*
t
CK2
,
DQs
CAS latency = 2
t
CK3
,
DQs
CAS latency = 3
Begin Auto-precharge
*
Bank can be reactivated at completion of t
RP
.
t
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
DOUT A
0
DOUT A
0
NOP
(Burst Length = 1, CAS Latency = 2, 3)
相關(guān)PDF資料
PDF描述
IBMN325804CT3 256Mb（8Mbit x 8 I/O x 4 Bank） Synchronous DRAM(256M位（8M位 x 8 I/O x 4 組）同步動(dòng)態(tài)RAM)
IBMN325164CT3 256Mb（16Mbit x 4 I/O x 4 Bank） Synchronous DRAM(256M位（16M位 x 4 I/O x 4 組）同步動(dòng)態(tài)RAM)
IBMN612404GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
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