參數(shù)資料
型號: IBMN325404CT3
廠商: IBM Microeletronics
英文描述: 256Mb(4Mbit x 16 I/O x 4 Bank) Synchronous DRAM(256M位(4M位 x 16 I/O x 4 組)同步動態(tài)RAM)
中文描述: 256Mb的(的4Mb × 16的I / O × 4行)同步DRAM(256M位(4分位× 16的I / O × 4組)同步動態(tài)RAM)的
文件頁數(shù): 37/66頁
文件大?。?/td> 1699K
代理商: IBMN325404CT3
IBMN325164CT3
IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
06K0608.F39375A
10/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 37 of 66
AC Characteristics
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
1. An initial pause of 200
μ
s, with DQM and CKE held high, is required after power-up. A Precharge All
Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after
the Mode Register Set operation.
2. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
4. Load Circuit A: AC timing tests have V
IL
= 0.4 V and V
IH
= 2.4 V with the timing referenced to the 1.40V
crossover point
5. Load Circuit A: AC measurements assume t
T
= 1.0ns.
6. Load Circuit B: AC timing tests have V
IL
= 0.8 V and V
IH
= 2.0 V with the timing referenced to the 1.40V
crossover point
7. Load Circuit B: AC measurements assume t
T
= 1.2ns.
.
AC Characteristics Diagrams
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
1.4V
V
IL
1.4V
t
T
Vtt = 1.4V
Output
50
50pF
Z
o
= 50
AC Output Load Circuit (A)
t
CKH
t
CKL
Output
50pF
Z
o
= 50
AC Output Load Circuit (B)
V
IH
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