參數(shù)資料
型號: IBMN325804CT3
廠商: IBM Microeletronics
英文描述: 256Mb(8Mbit x 8 I/O x 4 Bank) Synchronous DRAM(256M位(8M位 x 8 I/O x 4 組)同步動(dòng)態(tài)RAM)
中文描述: 256Mb的(8Mbit × 8的I / O × 4行)同步DRAM(256M位(800萬位× 8的I / O × 4組)同步動(dòng)態(tài)RAM)的
文件頁數(shù): 12/66頁
文件大?。?/td> 1699K
代理商: IBMN325804CT3
IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 66
06K0608.F39375A
10/00
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a
high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first
or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that
point the Write Command will have control of the DQ bus.
Minimum Read to Write Interval
COMMAND
NOP
NOP
READ A
WRITE A
NOP
NOP
NOP
DQM
DIN A
0
DIN A
1
DIN A
2
DIN A
3
: “H” or “L”
DIN A
0
DIN A
1
DIN A
2
DIN A
3
t
CK2
,
DQs
CAS latency = 2
t
CK3
,
DQs
CAS latency = 3
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
(Burst Length = 4, CAS latency = 2, 3)
DQM high for CAS latency = 2 only.
Required to mask first bit of READ data.
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