參數(shù)資料
型號(hào): IBMN325804CT3
廠商: IBM Microeletronics
英文描述: 256Mb(8Mbit x 8 I/O x 4 Bank) Synchronous DRAM(256M位(8M位 x 8 I/O x 4 組)同步動(dòng)態(tài)RAM)
中文描述: 256Mb的(8Mbit × 8的I / O × 4行)同步DRAM(256M位(800萬位× 8的I / O × 4組)同步動(dòng)態(tài)RAM)的
文件頁數(shù): 22/66頁
文件大?。?/td> 1699K
代理商: IBMN325804CT3
IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 22 of 66
06K0608.F39375A
10/00
Burst Read Followed by the Precharge Command
Burst Write Followed by the Precharge Command
COMMAND
READ Ax
0
NOP
NOP
NOP
NOP
NOP
NOP
*
NOP
t
CK2
,
DQs
CAS latency = 3
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT Ax
0
DOUT Ax
1
DOUT Ax
2
DOUT Ax
3
Precharge A
t
RP
Bank A can be reactivated at completion of t
RP
.
t
RP
is a function of clock cycle and speed sort.
*
(Burst Length = 4, CAS Latency = 3)
COMMAND
NOP
NOP
NOP
*
WRITE Ax
0
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
DIN Ax
0
DIN Ax
1
Bank can be reactivated at completion of t
.
t
DPL
and t
RP
are functions of clock cycle and speed sort.
See the Clock Frequency and Latency table.
*
Activate
Bank Ax
t
CK2,
DQs
CAS latency = 2
t
DPL
t
RP
Precharge A
(Burst Length = 2, CAS Latency = 2)
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IBMN325164CT3 256Mb(16Mbit x 4 I/O x 4 Bank) Synchronous DRAM(256M位(16M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM)
IBMN612404GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM(采用雙數(shù)據(jù)速率結(jié)構(gòu)))
IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM(采用雙數(shù)據(jù)速率結(jié)構(gòu)))
IBMN625404GT3B 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
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