參數(shù)資料
型號: IBMN325804CT3
廠商: IBM Microeletronics
英文描述: 256Mb(8Mbit x 8 I/O x 4 Bank) Synchronous DRAM(256M位(8M位 x 8 I/O x 4 組)同步動態(tài)RAM)
中文描述: 256Mb的(8Mbit × 8的I / O × 4行)同步DRAM(256M位(800萬位× 8的I / O × 4組)同步動態(tài)RAM)的
文件頁數(shù): 24/66頁
文件大?。?/td> 1699K
代理商: IBMN325804CT3
IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 24 of 66
06K0608.F39375A
10/00
Burst write operations will be terminated by the Precharge command. The last write data that will be properly
stored in the device is that write data that is presented to the device a number of clock cycles prior to the Pre-
charge command equal to the Data-in to Precharge delay, t
DPL
.
Precharge Termination of a Burst Write
COMMAND
NOP
NOP
NOP
WRITE Ax
0
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
DIN Ax
1
DIN Ax
2
t
DPL
DIN Ax
0
t
CK2
,
DQs
CAS latency = 2
NOP
DIN Ax
1
DIN Ax
2
DIN Ax
0
t
CK3
,
DQs
CAS latency = 3
DQM
Precharge A
t
DPL
is an asynchronous timing and may be completed in one or two clock cycles
depending on clock cycle time.
(Burst Length = 8, CAS Latency = 2, 3)
t
DPL
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