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參數(shù)資料
| 型號(hào)： | IBMN325804CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb（8Mbit x 8 I/O x 4 Bank） Synchronous DRAM(256M位（8M位 x 8 I/O x 4 組）同步動(dòng)態(tài)RAM) |
| 中文描述： | 256Mb的（8Mbit × 8的I / O × 4行）同步DRAM（256M位（800萬(wàn)位× 8的I / O × 4組）同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 26/66頁(yè) |
| 文件大?。?/td> | 1699K |
| 代理商： | IBMN325804CT3 |
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IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 26 of 66
06K0608.F39375A
10/00
Power Down Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active
Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the neces-
sary precharge delay (t
RP
) must occur before the SDRAM can enter the power down mode. If a bank is acti-
vated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a
Power Down Mode Command when the device is performing a Read or Write operation causes the device to
enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initi-
ated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does
not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the
Refresh period (t
REF
) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or
Device Deselect Command) is required on the next rising clock edge.
Power Down Mode Exit Timing
COMMAND
NOP
COMMAND
NOP
NOP
NOP
NOP
NOP
CKE
: “H” or “L”
CK
Tm
Tm+2
Tm+1
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+ 8
t
CES(min)
t
CK
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