參數(shù)資料
型號(hào)： IBMN325804CT3
廠商： IBM Microeletronics
英文描述： 256Mb（8Mbit x 8 I/O x 4 Bank） Synchronous DRAM(256M位（8M位 x 8 I/O x 4 組）同步動(dòng)態(tài)RAM)
中文描述： 256Mb的（8Mbit × 8的I / O × 4行）同步DRAM（256M位（800萬(wàn)位× 8的I / O × 4組）同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 36/66頁(yè)
文件大?。?/td> 1699K
代理商： IBMN325804CT3
IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 36 of 66
06K0608.F39375A
10/00
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Speed
Units
Notes
-75H
-75D
-75A
-260
-360
-10
Operating Current
I
CC1
1 bank operation
t
= t
(min), t
= min
Active-Precharge command
cycling without burst operation
130
130
120
115
115
90
mA
1, 2, 3
Precharge Standby Current
in Power Down Mode
I
CC2P
CKE
≤
V
IL
(max), t
CK
= min,
CS = V
IH
(min)
CKE
≤
V
IL
(max), t
CK
= Infinity,
CS = V
IH
(min)
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
I
CC2NS
CKE
≥
V
IH
(min), t
CK
= Infinity,
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
I
CC3P
CKE
≤
V
IL
(max), t
CK
= min,
t
= min,
Read/ Write command cycling,
Multiple banks active, gapless
data, BL = 4
2
2
2
2
2
2
mA
1
I
CC2PS
2
2
2
2
2
2
mA
1
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
30
30
30
20
20
20
mA
1, 5
8
8
8
8
8
8
mA
1, 7
No Operating Current
(Active state: 4 bank)
I
CC3N
60
60
60
45
45
45
mA
1, 5
6
6
6
6
6
6
mA
1, 6
Operating Current (Burst
Mode)
I
CC4
120
120
120
90
90
90
mA
1, 3, 4
Auto (CBR) Refresh Current
I
CC5
t
= min, t
= t
(min)
CBR command cycling
175
175
175
155
155
140
mA
1
Self Refresh Current
I
CC6
CKE
≤
0.2V
3
3
3
3
3
3
mA
1
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the
other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
. Input
signals are changed up to three times during t
RC
(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during t
CK
(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
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