參數(shù)資料
型號(hào)： IBMN612404GT3B
廠商： IBM Microeletronics
英文描述： 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
中文描述： 128Mb的雙數(shù)據(jù)速率同步DRAM（128兆位高速的CMOS同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（采用雙數(shù)據(jù)速率結(jié)構(gòu)））
文件頁數(shù)： 78/79頁
文件大?。?/td> 1324K
代理商： IBMN612404GT3B
IBMN612404GT3B
IBMN612804GT3B
128Mb Double Data Rate Synchronous DRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 78 of 79
06K0566.F39350B
1/01
10/00
Changed to Preliminary classification.
Changed nomenclature for “PC”200 to “DDR”200.
Updated ordering information.
Clarified DM definition during a write.
Updated power sequencing requirements for DRAM initialization.
Updated CK and CK input capacitance. Added V-I matching ratio.
Changed “Weak” to “Half” to match JEDEC terminology.
Removed Note from Half-Strength driver notes indicating SSTC compatibility.
Inserted DQS/DQ/DM Slew Rate table.
Updated I
DD5.
Added I
DD7
current term as defined at JEDEC.
Moved all notes to a table behind the AC parameters.
Updated t
CK
max to 12ns for all speed sorts.
Updated AC timing parameters to reflect the correct refresh rate.
Updated CL=2 support for the 75N device to be t
CKmin
=10ns.
Added notes 18 and 19 to t
DS
and t
DH
to describe derating curves for these parameters.
Added note 17 to t
IH
and t
IS
to describe derating curves for these parameters.
Updated Note 14 to indicate tester characterization.
Redefined t
DAL
specification, added note 16 to clarify.
Removed repetitive info from the AC timing table expressed in clock cycles.
1/01
Removed all reference to half strength drivers.
Updated the extended mode register definition to indicate A
1
=1 is reserved.
Removed V
IX
(DC) to be consistent with the industry standard DDR specification.
Revision Log
Rev
Contents of Modification
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IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
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