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| 型號： | IBMN612804GT3B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）) |
| 中文描述： | 128Mb的雙數(shù)據(jù)速率同步DRAM（128兆位高速的CMOS同步動態(tài)隨機存儲器（采用雙數(shù)據(jù)速率結(jié)構(gòu)）） |
| 文件頁數(shù)： | 52/79頁 |
| 文件大?。?/td> | 1324K |
| 代理商： | IBMN612804GT3B |
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IBMN612404GT3B
IBMN612804GT3B
128Mb Double Data Rate Synchronous DRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 52 of 79
06K0566.F39350B
1/01
Capacitance
Parameter
Symbol
Min.
Max.
Units
Notes
Input Capacitance: CK, CK
CI
1
2.0
3.0
pF
1
Delta Input Capacitance: CK, CK
delta CI
1
0.25
pF
1
Input Capacitance: All other input-only pins (except DM)
CI
2
2.0
3.0
pF
1
Delta Input Capacitance: All other input-only pins (except DM)
delta CI
2
0.5
pF
1
Input/Output Capacitance: DQ, DQS, DM
C
IO
4.0
5.0
pF
1, 2
Delta Input/Output Capacitance: DQ, DQS, DM
delta C
IO
0.5
pF
1
Output Capacitance: QFC
CO
1
2.0
4.0
pF
1
1. V
DDQ
= V
DD
= 2.5V 0.2V (minimum range to maximum range), f = 100MHz, T
A
= 25
°
C, VO
DC
= V
DDQ/2
, VO
Peak -Peak
= 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This
is required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
(0C
≤
T
A
≤
70
°
C; V
DDQ
= 2.5V
±
0.2V, V
DD
=
+
2.5V
±
0.2V, see AC Characteristics)
Symbol
Parameter
Min
Max
Units
Notes
V
DD
Supply Voltage
2.3
2.7
V
1
V
DDQ
I/O Supply Voltage
2.3
2.7
V
1
V
SS
, V
SSQ
Supply Voltage
I/O Supply Voltage
0
0
V
V
REF
I/O Reference Voltage
0.49 x V
DDQ
0.51 x V
DDQ
V
1, 2
V
TT
I/O Termination Voltage (System)
V
REF
0.04
V
REF
+
0.04
V
1, 3
V
IH(DC)
Input High (Logic1) Voltage
V
REF
+
0.15
V
DDQ
+
0.3
V
1
V
IL(DC)
Input Low (Logic0) Voltage
0.3
V
REF
0.15
V
1
V
IN(DC)
Input Voltage Level, CK and CK Inputs
0.3
V
DDQ
+
0.3
V
1
V
ID(DC)
Input Differential Voltage, CK and CK Inputs
0.30
V
DDQ
+
0.6
V
1, 4
VI
Ratio
V-I Matching Pullup Current to Pulldown Current Ratio
0.71
1.4
5
I
I
Input Leakage Current
Any input 0V
≤
V
IN
≤
V
DD
; (All other pins not under test
=
0V)
5
5
μ
A
1
I
OZ
Output Leakage Current
(DQs are disabled; 0V
≤
V
out
≤
V
DDQ
5
5
μ
A
1
I
OH
Output Current: Nominal Strength Driver
High current (V
OUT
= V
DDQ
-0.373V, min V
REF
, min V
TT
)
Low current (V
OUT
= 0.373V, max V
REF
, max V
TT
)
16.8
mA
1
I
OL
16.8
1. Inputs are not recognized as valid until V
REF
stabilizes.
2. V
REF
is expected to be equal to 0.5 V
DDQ
of the transmitting device, and to track variations in the DC level of the same. Peak-to-
peak noise on V
REF
may not exceed 2% of the DC value.
3. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
,
and must track variations in the DC level of V
REF
.
4. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK
.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-
ture and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum
difference between pullup and pulldown drivers due to process variation.
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