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| 型號： | IBMN612804GT3B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動態(tài)RAM（采用雙數(shù)據(jù)速率結構）) |
| 中文描述： | 128Mb的雙數(shù)據(jù)速率同步DRAM（128兆位高速的CMOS同步動態(tài)隨機存儲器（采用雙數(shù)據(jù)速率結構）） |
| 文件頁數(shù)： | 63/79頁 |
| 文件大?。?/td> | 1324K |
| 代理商： | IBMN612804GT3B |
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IBMN612404GT3B
IBMN612804GT3B
Preliminary
128Mb Double Data Rate Synchronous DRAM
06K0566.F39350B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 63 of 79
Electrical Characteristics & AC Timing for DDR266B - Applicable Specifications
Expressed in Clock Cycles
(0
°
C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC
Characteristics)
Symbol
Parameter
DDR266B @ CL = 2.5
Units
Notes
Min
Max
t
MRD
Mode register set command cycle time
2
t
CK
1, 2, 3, 4
t
WPRE
Write preamble
0.25
t
CK
1, 2, 3, 4
t
RAS
Active to Precharge command
6
16000
t
CK
1, 2, 3, 4
t
RC
Active to Active/Auto-refresh command period
9
t
CK
1, 2, 3, 4
t
RFC
Auto-refresh to Active/Auto-refresh
command period
10
t
CK
1, 2, 3, 4
t
RCD
Active to Read or Write delay
3
t
CK
1, 2, 3, 4
t
RAP
Active to Read Command with Autoprecharge
3
t
CK
1, 2, 3, 4
t
RP
Precharge command period
3
t
CK
1, 2, 3, 4
t
RRD
Active bank A to Active bank B command
2
t
CK
1, 2, 3, 4
t
WR
Write recovery time
2
t
CK
1, 2, 3, 4
t
DAL
Auto precharge write recovery + precharge time
5
t
CK
1, 2, 3, 4,
5
t
WTR
Internal write to read command delay
1
t
CK
1, 2, 3, 4
t
XSNR
Exit self-refresh to non-read command
10
t
CK
1, 2, 3, 4
t
XSRD
Exit self-refresh to read command
200
t
CK
1, 2, 3, 4
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK, is V
REF.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
TT
.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
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