參數(shù)資料
型號(hào)： IBMN612804GT3B
廠商： IBM Microeletronics
英文描述： 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
中文描述： 128Mb的雙數(shù)據(jù)速率同步DRAM（128兆位高速的CMOS同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（采用雙數(shù)據(jù)速率結(jié)構(gòu)））
文件頁(yè)數(shù)： 77/79頁(yè)
文件大?。?/td> 1324K
代理商： IBMN612804GT3B
IBMN612404GT3B
IBMN612804GT3B
Preliminary
128Mb Double Data Rate Synchronous DRAM
06K0566.F39350B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 77 of 79
Revision Log
Rev
Contents of Modification
6/1/99
Initial release; Rev 0.0
04/06/00
1st Revision; Rev 0.1.
Deleted reference to x16 organization.
Corrected typo in Features section. Avg period refresh interval is 15.6
μ
s not 7.8ns.
Added note to pinout that QFC\ is an optional feature and must be specified upon purchasing.
Modified AC and DC operating conditions for V
ix
, I
ol
, I
oh
, V
ref
. Added Iolw and Iohw DC parameters.
Added DDR device labeling guild to device ordering information.
Added p/n’s for devices that support the QFC\ option.
Clarified description of Extended mode register, DLL Enable/Disable, Output drive strength, and QFC\ Enable
/Disable.
Added note to Pinout diagrams that QFC\ is an optional feature and must be specified via p/n when ordering
devices.
Removed the word “optional” from the Drive Strength Field in the Extended Mode Register Definition Diagram.
Changed Vil (DC) and V
ih
(DC) to V
ref
-0.15V and V
ref
+0.15V, respectively.
Changed Vil (AC) and V
ih
(AC) to V
ref
-0.31V and V
ref
+0.31V, respectively.
Added Idd values for PC200 and PC266 speed sorts.
Removed t
DQSQ
(min) and t
DQSQA
(min) from AC timing parameters.
Changed AC Timing Load Circuit diagram and added QFC\ Timing Load Circuit diagram.
Added t
IPW
parameter to AC timings and modified t
IS
& t
IH
to reflect slow and fast input slew rates.
Changed Input capacitance for all inputs and outputs (except CK and CK\).
Added delta input capacitance specification for all inputs and outputs (except QFC\)
AC Operating Characteristics: changed definition of Vix from input “closing” point to input “crossing” point.
Added new AC timing parameter (t
HP
).
Replaced AC timing parameter t
DV
with t
QH
Modified Dataout Read Timing Diagram to remove reference to t
DV
and replace with t
HP
and t
QH
.
Changed RAS, CAS, and WE to RAS, CAS, and WE where applicable.
Added further clarification to “Initialization” description.
Added
t
RAS
lockout description under auto precharge description with supporting timing diagram.
Added t
RAP
as a new parameter to AC timing parameters.
Added t
RAS
lock out support to Features section.
Removed statement from Auto Refresh section that states “a maximum of 8 auto refresh commands can be
posted in the system”.
Corrected Data Input / Output Timing Diagram (tDSL-> tDQSL and tDSH-> tDQSH)
5/12/00
2nd Revision.
Changed part number speed sort designator from 10H->8N, 8E->75N, 75E->7N.
Changed NU to DNU for correct JEDEC nomenclature.
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