參數(shù)資料
型號： IBMN625404GT3B
廠商： IBM Microeletronics
英文描述： 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM)
中文描述： 256MB雙數(shù)據(jù)速率同步DRAM（256M位雙數(shù)據(jù)速率同步動態(tài)RAM）的
文件頁數(shù)： 13/79頁
文件大小： 1328K
代理商： IBMN625404GT3B
IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 79
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these addi-
tional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output
enable/disable, bit A2 (IBM optional). These functions are controlled via the bit settings shown in the
Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set
command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the
device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements
result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The
DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit
of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the inter-
nal clock to lock to the externally applied clock before a Read command can be issued. This is the reason for
introducing timing parameter t
XSRD
for DDR SDRAM’s (Exit Self Refresh to Read Command). Non- Read
commands can be issued 2 clocks after the DLL is enabled via the EMRS command (t
MRD
) or 10 clocks after
the DLL is enabled via self refresh exit command (t
XSNR
, Exit Self Refresh to Non-Read Command).
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II.
QFC Enable/Disable
The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system
memory bus by means of external FET switches when the given module (DIMM) is not being accessed. The
QFC function is an optional feature for IBM and is not included on all DDR SDRAM devices. Refer to the DDR
SDRAM Device Labeling Table for proper differentiation when ordering DDR devices with or without the QFC
function. The QFC output is an open drain driver and must be connected to V
DDQ
through a pull up resistor at
the board level if the QFC function is enabled. The recommended pull up resistance is 150 ohms.
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