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| 型號： | IBMN625404GT3B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM) |
| 中文描述： | 256MB雙數(shù)據(jù)速率同步DRAM（256M位雙數(shù)據(jù)速率同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 19/79頁 |
| 文件大小： | 1328K |
| 代理商： | IBMN625404GT3B |
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IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 19 of 79
Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank
must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and
BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row
to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued
to that row, subject to the t
RCD
specification. A subsequent Active command to a different row in the same
bank can only be issued after the previous active row has been “closed” (precharged). The minimum time
interval between successive Active commands to the same bank is defined by t
RC
. A subsequent Active com-
mand to another bank can be issued while the first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval between successive Active commands to different
banks is defined by t
RRD
.
Activating a Specific Row in a Specific Bank
RA
BA
HIGH
RA = row address.
BA = bank address.
CK
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
Don’t Care
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