參數(shù)資料
型號: IBMN625404GT3B
廠商: IBM Microeletronics
英文描述: 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述: 256MB雙數(shù)據(jù)速率同步DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)的
文件頁數(shù): 37/79頁
文件大?。?/td> 1328K
代理商: IBMN625404GT3B
IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 37 of 79
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
t
DQSS
(max)
Maximum D
QSS
NOP
NOP
NOP
Read
Write
NOP
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
t
WTR
is referenced from the first positive CK edge after the last data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
DIa- b
CK
CK
Command
Address
DQS
DQ
DM
Don’t Care
BAa, COL b
BAa, COL n
t
WTR
CL = 2
T1
T2
T3
T4
T5
T6
Minimum D
QSS
NOP
NOP
NOP
Read
Write
NOP
CK
CK
Command
Address
BAa, COL b
BAa, COL n
t
WTR
DI a-b
DQS
DQ
DM
CL = 2
t
DQSS
(min)
1
1
1
1
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