參數(shù)資料
型號(hào): IBMN625404GT3B
廠商: IBM Microeletronics
英文描述: 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述: 256MB雙數(shù)據(jù)速率同步DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)的
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代理商: IBMN625404GT3B
IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 64 of 79
29L0011.E36997B
1/01
Data Input (Write)
(Timing Burst Length = 4)
Data Output (Read)
(Timing Burst Length = 4)
t
DH
t
DS
t
DH
t
DS
t
DSL
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
DI n
DQS
DQ
DM
Don’t Care
t
DSH
t
DQSQ
(max)occurs when DQS is the earliest among DQS and DQ signals to transition.
DQS
DQ
t
DQSQ
t
DQSQ
t
QH1
Data Output hold time from Data Strobe is shown as t
QH
. t
is a function of the clock high or low time (t
HP
)
for that given clock cycle. Note correlation of t
HP
to t
QH
in the diagram above (t
HP1
to t
QH1
, etc.).
t
QH2
t
DQSQ
t
QH3
t
QH4
t
DQSQ
CK
CK
t
HP
t
HP
t
HP
t
HP1
t
HP2
t
HP3
t
HP4
t
is the half cycle pulse width for each half cycle clock. t
HP
is referenced to the clock duty cycle only
and not to the data strobe (DQS) duty cycle.
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