參數(shù)資料
型號: IBMN625804GT3B
廠商: IBM Microeletronics
英文描述: 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM)
中文描述: 256MB雙數(shù)據(jù)速率同步DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM)的
文件頁數(shù): 12/79頁
文件大小: 1328K
代理商: IBMN625804GT3B
IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 79
29L0011.E36997B
1/01
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command
with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode
Register Set command issued to reset the DLL should always be followed by a Mode Register Set command
to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
CAS Latencies
NOP
NOP
NOP
NOP
NOP
Read
CAS Latency = 2, BL = 4
Shown with nominal t
AC
, t
DQSCK
, and t
DQSQ
.
CK
CK
Command
DQS
DQ
Don’t Care
CL=2
NOP
NOP
NOP
NOP
NOP
Read
CAS Latency = 2.5, BL = 4
CK
CK
Command
DQS
DQ
CL=2.5
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