參數(shù)資料
型號(hào)： IBMN625804GT3B
廠商： IBM Microeletronics
英文描述： 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述： 256MB雙數(shù)據(jù)速率同步DRAM（256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 3/79頁(yè)
文件大?。?/td> 1328K
代理商： IBMN625804GT3B
IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 79
Input/Output Functional Description
Symbol
Type
Function
CK, CK
Input
Clock:
CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data
is referenced to the crossings of CK and CK (both directions of crossing).
CKE, CKE0, CKE1
Input
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asyn-
chronous for self refresh exit. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input
buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one
CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facil-
itate independent power down control of stacked devices.
CS, CS0, CS1
Input
Chip Select:
All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different
pin, in addition to CS0, to allow upper or lower deck selection on stacked devices.
RAS, CAS, WE
Input
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
DM
Input
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM
is sampled high coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. During a Read, DM can be driven high, low, or floated.
BA0, BA1
Input
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Pre-
charge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
A0 - A12
Input
Address Inputs:
Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/Write commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank
is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the
op-code during a Mode Register Set command.
DQ
Input/Output
Data Input/Output:
Data bus.
DQS
Input/Output
Data Strobe:
Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.
QFC
Output
FET control
: Optional. Output during every Read and Write access. Is provided to control
isolation switches on modules. Open drain output. Pullup resistor connected to V
DDQ
must be
supplied at second level of assembly.
NC
No Connect:
No internal electrical connection is present.
NU
Electrical connection is present. Should not be connected at second level of assembly.
V
DDQ
V
SSQ
V
DD
V
SS
V
REF
Supply
DQ Power Supply:
2.5V
±
0.2V.
Supply
DQ Ground
Supply
Power Supply:
2.5V
±
0.2V.
Supply
Ground
Supply
SSTL_2 reference voltage:
(V
DDQ
/ 2)
±
1%.
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