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參數(shù)資料
| 型號： | IBMN625804GT3B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM) |
| 中文描述： | 256MB雙數(shù)據(jù)速率同步DRAM（256M位雙數(shù)據(jù)速率同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 45/79頁 |
| 文件大?。?/td> | 1328K |
| 代理商： | IBMN625804GT3B |
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IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 45 of 79
Power-Down
Power-down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs
when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there
is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates
the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for
maximum power savings, the user has the option of disabling the DLL prior to entering Power-down. In that
case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a Read
command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at
the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is
limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred
over the DLL-disabled power-down mode.
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect
command). A valid, executable command may be applied one clock cycle later.
Power Down
t
IS
t
IS
CK
CK
CKE
Command
No column
access in
progress
VALID
NOP
VALID
Don’t Care
Exit
power down
mode
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
NOP
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