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參數資料
| 型號： | IBMN625804GT3B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb Double Data Rate Synchronous DRAM(256M位雙數據速率同步動態(tài)RAM) |
| 中文描述： | 256MB雙數據速率同步DRAM（256M位雙數據速率同步動態(tài)RAM）的 |
| 文件頁數： | 57/79頁 |
| 文件大小： | 1328K |
| 代理商： | IBMN625804GT3B |
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IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 57 of 79
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, I
DD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I
DD
tests may use a V
IL
to V
IH
swing of up to 1.5V in the test environment, but input timing is still refer-
enced to V
REF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC
input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between
V
IL(AC)
and V
IH(AC)
.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not
ring back above (below) the DC input low (high) level.
AC Output Load Circuit Diagrams
50
Timing Reference Point
Output
(V
OUT
)
30pF
V
TT
150
Timing Reference Point
QFC
(V
OUT
)
15pF
V
DDQ
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