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| 型號： | IBMN625804GT3B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM) |
| 中文描述： | 256MB雙數(shù)據(jù)速率同步DRAM（256M位雙數(shù)據(jù)速率同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 58/79頁 |
| 文件大?。?/td> | 1328K |
| 代理商： | IBMN625804GT3B |
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IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 58 of 79
29L0011.E36997B
1/01
AC Input Operating Conditions
(0 C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
V
IH(AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
V
REF
+ 0.31
V
1, 2
V
IL(AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
V
REF
0.31
V
1, 2
V
ID(AC)
Input Differential Voltage, CK and CK Inputs
0.62
V
DDQ
+ 0.6
V
1, 2, 3
V
IX(AC)
Input Crossing Point Voltage, CK and CK Inputs
0.5*V
DDQ
0.2 0.5*V
DDQ
+
0.2
V
1, 2, 4
1. Input slew rate = 1V/ns
.
2. Inputs are not recognized as valid until V
REF
stabilizes.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
I
DD
Specifications and Conditions
(0 C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
DDR200
(8N)
t
CK
=10ns
DDR266A/B
(7N/75N)
t
CK
=7.5ns
Unit
Notes
I
DD0
Operating Current
: one bank; active / precharge; t
= t
(min); DQ, DM,
and DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
75
85
mA
1
I
DD1
Operating Current
: one bank; active / read / precharge; Burst = 2; t
= t
RC
(min); CL = 2.5; I
OUT
= 0mA; address and control inputs changing once per
clock cycle
90
110
mA
1
I
DD2P
Precharge Power-Down Standby Current
: all banks idle; power-down
mode; CKE
≤
V
IL
(max)
15
15
mA
1
I
DD2N
Idle Standby Current:
CS
≥
V
(min); all banks idle; CKE
≥
V
IH
(min);
address and control inputs changing once per clock cycle
30
35
mA
1
I
DD3P
Active Power-Down Standby Current
: one bank active; power-down mode;
CKE
≤
V
IL
(max)
15
15
mA
1
I
DD3N
Active Standby Current
: one bank; active / precharge; CS
≥
V
(min);
CKE
≥
V
(min); t
= t
(max); DQ, DM, and DQS inputs changing twice
per clock cycle; address and control inputs changing once per clock cycle
50
60
mA
1
I
DD4R
Operating Current:
one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; I
OUT
= 0mA
130
165
mA
1
I
DD4W
Operating Current
: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs chang-
ing twice per clock cycle; CL = 2.5
115
150
mA
1
I
DD5
Auto-Refresh Current
: t
RC
= t
RFC
(min)
160
170
mA
1
I
DD6
Self-Refresh Current
: CKE
≤
0.2V
2
2
mA
1, 2
I
DD7
Operating current
: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every trans-
fer; t
RC
= t
RC
(min); I
OUT
= 0mA.
TBD
TBD
mA
1
1. I
DD
specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
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