參數(shù)資料
型號(hào): IBMN625804GT3B
廠商: IBM Microeletronics
英文描述: 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述: 256MB雙數(shù)據(jù)速率同步DRAM(256M位雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)的
文件頁數(shù): 6/79頁
文件大小: 1328K
代理商: IBMN625804GT3B
IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 79
29L0011.E36997B
1/01
Block Diagram (64Mb x 4)
R
1
DQS
CK, CK
DLL
RAS
CAS
CK
CS
WE
CK
C
Column-Address
Counter/Latch
Mode
Registers
11
C
D
A0-A12,
BA0, BA1
CKE
13
15
I/O Gating
DM Mask Logic
Array
(8192 x 1024 x 8)
Sense Amplifiers
Bank1
Bank2
Bank3
13
10
1
2
2
R
4
4
4
RInput
1
1
1
1
1
8
8
2
8
clk
Data
Mask
Data
CK,
CK
COL0
COL0
COL0
clk
in
M
GeDQS
4
4
4
4
4
8
DQ0-DQ3,
DM
DQS
1
R
Write
FIFO
Dri&
Note:
This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note:
DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Column
Decoder
(x8)
R
1
8
B
R
&
8192
A
D
B
QFC
generator
DRVR
QFC
(Optional)
15
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