參數(shù)資料
型號： IBMN625804GT3B
廠商： IBM Microeletronics
英文描述： 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM)
中文描述： 256MB雙數(shù)據(jù)速率同步DRAM（256M位雙數(shù)據(jù)速率同步動態(tài)RAM）的
文件頁數(shù)： 61/79頁
文件大?。?/td> 1328K
代理商： IBMN625804GT3B
IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 61 of 79
Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is V
REF.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteris-
tics (Note 3) is V
TT
.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parame-
ters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or
begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for
this parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before
this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of
the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to
logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to
low at this time, depending on t
DQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. QFC is enabled as soon as possible after the rising CK edge that registers the Write command.
10. QFC is disabled as soon as possible after the last valid DQS edge transitions Low.
11. For command/address input slew rate
≥
1.0V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
12. For command/address input slew rate
≥
0.5V/ns and < 1.0V/ns. Slew rate is measured between V
OH
(AC)
and V
OL
(AC).
13. CK/CK slew rates are
≥
1.0V/ns.
14. These parameters guarantee device timing, but they are not necessarily tested on each device, and they
may be guaranteed by design or tester characterization.
15. The specified timing is guaranteed assuming QFC is connected to a test load consisting of 20pF to
ground and a pull up resistor of 150 ohms to V
ddq
.
16. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t
CK
is
equal to the actual system clock cycle time. For example, for DDR266B at CL = 2.5, t
DAL
= (15ns/7.5ns) +
(20ns/7.5ns) = 2 + 3 = 5.
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