參數(shù)資料
型號: MT9075A
廠商: Mitel Networks Corporation
英文描述: E1 Single Chip Transceiver
中文描述: 素E1單芯片收發(fā)器
文件頁數(shù): 33/78頁
文件大?。?/td> 1008K
代理商: MT9075A
Preliminary Information
MT9075A
4-161
Table 20 - National Use Bit Interrupt Mask Word
(Page 01H, Address 19H)
Bit
Name
Functional Description
7
TAIS
Transmit Alarm Indication Signal.
If one, an all ones signal is
transmitted. TAIS=0 for normal
operation.
6
TAIS0
Transmit AIS Time Slot Zero.
If
one,
an
all
ones
transmitted in time slot zero. If zero,
time slot zero functions normally.
signal
is
5
TAIS16
Transmit AIS Time Slot 16.
If one,
an all ones signal is transmitted in
time slot 16. If zero, time slot
functions normally.
4
TE
Transmit E bits.
When zero and
CRC-4
synchronization
achieved, the E-bits transmit the
received CRC-4 comparison results
to the distant end of the link, as per
G.704. That is, when zero and
CRC-4 synchronization is lost, the
transmit E-bits will be zero. If one,
and CRC-4 synchronization is lost
the transmit E-bits will be one.
is
3
REFRM
Reframe.
If one for at least one
frame, and then cleared, the device
will initiate a search for a new basic
frame position. Reframing function
is activated on the one-to-zero
transition of the REFRM bit.
2
64KSEL
64 KHz Select.
If one, a 64 KHz
signal divided down from the
extracted received 2048 kbit/sec.
clock is output on RxFP/Rx64KCK
(pin 47 in PLCC, 35 in MQFP). If
zero that pin outputs an 8 KHz
signal derived from the extracted
clock.
1
DSToDE
DSTo Data Enable.
If zero, DSTo is
enabled. If one, DSTo will be
tristated if one of the following
conditions exists: LIU loss of signal,
loss
of
terminal
(SYNC=1), loss of CRC4 sync
(CRCSYN=1) or AIS.
frame
sync
0
CSToDE
CSTo Data Enable.
If zero, CSTo is
enabled. If one, CSTo will be
tristated if one of the following
conditions exists: loss of multiframe
sync (MFSYNC=1), or AIS16 =1
Table 19 - Transmit Alarm Control Word
(Page 01H, Address 16H)
Bit
Name
Functional Description
7
---
Unused.
6
PRBSO
PRBS
Interrupt.
(PRBSO = 1), an interrupt is
initiated on overflow of PRBS
counter (page 04H, address 10H)
from FFH to 0H. Interrupt vector =
00000010.
Counter
When
Overflow
unmasked
5
PRBSI
PRBS Interrupt.
When unmasked
(PRBSI = 1), an interrupt is initiated
on a single PRBS detection error.
Interrupt vector = 00000010.
4
S
a
nibI
Changed S
a
Nibble Interrupt.
When unmasked (S
a
nibI = 1), an
interrupt
is
generated
detection of a change of state in any
of received S
a
nibbles (nibble S
a5
,
nibble S
a6
, nibble S
a7
or nibble S
a8
).
Interrupt vector = 00000010.
upon
3
S
a
bitI
Changed S
a
Bit Interrupt.
When
unmasked (S
a
bitI = 1), an interrupt
is generated upon detection of a
change of state in any of received
S
a
bits (S
a5
, S
a6
, S
a7
or S
a8
).
Interrupt vector = 00000010.
2
C8S
a6
I
Eight Consecutive S
a6
Nibble
Interrupt.
When unmasked (C8S
a6
I
= 1), an interrupt is generated upon
detection of the eighth consecutive
S
a6
nibble with the same pattern.
Interrupt vector = 00000010.
1
S
a6
I
Changed S
a6
Nibble Interrupt.
When unmasked (S
a6
I = 1), an
interrupt
is
generated
detection of a change of state in
received S
a6
nibbles. Interrupt
vector = 00000010.
upon
0
S
a5
I
Changed S
a5
Bit Interrupt.
When
unmasked (S
a5
I =1), an interrupt is
generated upon detection of a
change of state in the received S
a5
bit. Interrupt vector = 00000010.
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