參數(shù)資料
型號(hào)： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 78/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
78
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
PLL and PLL controller (continued)
Table 37. PLL Control/Status Register (PLLCSR) [0x01B7 C100]
31
28
27
24
23
20
19
16
Reserved
R
0
15
12
11
8
7
6
5
4
3
2
1
0
Reserved
STABLE
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R
0
R
x
R
0
RW
1
R/W
0
R/W
0b
RW
0
Legend:
R = Read only, R/W = Read/Write; -n = value after reset
Table 38. PLL Control/Status Register (PLLCSR) Description
BIT #
31:7
NAME
Reserved
DESCRIPTION
Reserved. Read-only, writes have no effect.
Clock Input Stable. This bit indicates if the clock input has stabilized.
0
–
Clock input not yet stable. Clock counter is not finished counting (default).
1
–
Clock input stable.
6
STABLE
5:4
Reserved
Reserved. Read-only, writes have no effect.
Asserts RESET to PLL
0
–
PLL Reset Released.
1
–
PLL Reset Asserted (default).
3
PLLRST
2
Reserved
Reserved. The user
must
write a “0” to this bit.
Select PLL Power Down
0
–
PLL Operational (default).
1
–
PLL Placed in Power-Down State.
1
PLLPWRDN
0
PLLEN
PLL Mode Enable
0
–
Bypass Mode (default). PLL disabled.
Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
directly from input reference clock.
PLL Enabled.
Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
from PLL output.
1
–
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