參數(shù)資料
型號(hào)： MPC8315EVRAGDA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封裝： 29 X 29 MM, 2.23 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-620
文件頁(yè)數(shù)： 3/112頁(yè)
文件大?。?/td> 1283K
代理商： MPC8315EVRAGDA
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
100
Freescale Semiconductor
Clocking
24.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 76 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 76 should be considered as reserved.
NOTE
Core VCO frequency = core frequency
× VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 400–800 MHz.
24.3
Suggested PLL Configurations
To simplify the PLL configurations, the MPC8315E might be separated into two clock domains. The first
domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are
configured separately. Both of the domains has one common input clock. Table 77 shows suggested PLL
configurations for 33, 25, and 66 MHz input clocks.
Table 76. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider1
1 Core VCO frequency = core frequency × VCO divider.
0–1
2–5
6
nn
0000
0
PLL bypassed
(PLL off,
csb_clk clocks core directly)
PLL bypassed
(PLL off,
csb_clk clocks core directly)
11
nnnn
nN/A
N/A
00
0001
01:1
2
01
0001
01:1
4
00
0001
11.5:1
2
01
0001
11.5:1
4
00
0010
02:1
2
01
0010
02:1
4
00
0010
12.5:1
2
01
0010
12.5:1
4
00
0011
03:1
2
01
0011
03:1
4
Table 77. Suggested PLL Configurations
Conf. No.
SPMF
Core\PLL
Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz)
1
0100
0000100
33.33
133.33
266.66
2
0100
0000101
25
100
250
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