參數(shù)資料
型號: AT32UC3L032-D3UR
廠商: Atmel
文件頁數(shù): 38/174頁
文件大?。?/td> 0K
描述: MCU AVR32 32KB FLASH 48TLLGA
標(biāo)準(zhǔn)包裝: 8,000
系列: AVR®32 UC3 L
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-UFLGA
包裝: 帶卷 (TR)
其它名稱: 32UC3L032-D3UR
32UC3L032-D3UR-ND
20
32099I–01/2012
AT32UC3L016/32/64
Figure 4-1.
Overview of the AVR32UC CPU
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 21 shows an overview of the AVR32UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
MPU
Hi
g
hSpee
dBus
Hi
g
hSpee
dBus
OCD
system
OC
D
in
te
rf
ac
e
In
te
rr
up
tco
nt
ro
ller
in
te
rfa
ce
High
Speed
Bus slave
Hi
g
hSpee
dBus
High Speed Bus master
Power/
Reset
control
Res
et
in
te
rfa
ce
CPU Local
Bus
master
CPU
Loc
a
lBus
Data memory controller
CPU RAM
High Speed
Bus master
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