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參數(shù)資料
| 型號(hào)： | IC42S16102-5TI |
| 英文描述： | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| 中文描述： | 為512k × 16位× 2銀行（16兆）內(nèi)存 |
| 文件頁(yè)數(shù)： | 29/78頁(yè) |
| 文件大小： | 790K |
| 代理商： | IC42S16102-5TI |
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IC42S16102
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005
29
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress, i.
e., before that cycle completes. Data corresponding to the
new write command can be input at the point new write
command is executed. To prevent collision between input
and output data at the I/On pins during this operation, the
output data must be masked using the U/LDQM pins. The
interval (t
CCD
) between these commands must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
CAS
latency = 2, 3, burst length = 4
WRITE B0
READ A0
COMMAND
U/LDQM
I/O
CLK
D
IN
B0
D
IN
B2
D
IN
B1
D
IN
B3
t
CCD
HI-Z
READ (CA=A, BANK 0)
WRITE (CA=B, BANK 0)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S16102-5TIG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6BG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6BIG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6T | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6TG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16102-5TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-6TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
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