參數(shù)資料
型號: IC42S16102-7TIG
英文描述: 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM
中文描述: 為512k × 16位× 2銀行(16兆)內(nèi)存
文件頁數(shù): 32/78頁
文件大小: 790K
代理商: IC42S16102-7TIG
IC42S16102
32
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IC42S16102 can output data continuously from the
burst start address (a) to location a+255 during a read
cycle in which the burst length is set to full page. The
IC42S16102 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (t
RAS
max.) following the burst stop
command.
CAS
Latency
3
2
t
RBD
3
2
After the period (t
RBD
) required for burst data output to stop
following the execution of the burst stop command has
elapsed, the outputs go to the HIGH impedance state. This
period (t
RBD
) is two clock cycle when the
CAS
latency is two
and three clock cycle when the
CAS
latency is three.
BST
READ A0
COMMAND
I/O
CLK
t
RBD
READ (CA=A, BANK 0)
BURST STOP
HI-Z
D
OUT
A0
D
OUT
A0
D
OUT
A1
D
OUT
A2
COMMAND
I/O
CLK
t
RBD
READ A0
READ (CA=A, BANK 0)
BURST STOP
BST
HI-Z
D
OUT
A0
D
OUT
A0
D
OUT
A1
D
OUT
A2
D
OUT
A3
D
OUT
A3
CAS
latency = 2, burst length = full page
CAS
latency = 3, burst length = full page
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