參數(shù)資料
型號(hào): IC42S16160-7TG
英文描述: 4M x 16Bit x 4 Banks (256-MBIT) SDRAM
中文描述: 4米× 16 × 4銀行(256兆)內(nèi)存
文件頁數(shù): 20/69頁
文件大?。?/td> 1219K
代理商: IC42S16160-7TG
IC42S16160
20
Integrated Circuit Solution Inc.
DR037-0A 9/05/2003
Precharge
The precharge command can be asserted anytime after t
RAS
(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters
the idle state after t
RP
(min.) is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as
follows.
PrechargeE
Burst lengh=4
T7
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
(t
RAS
is satisfied)
Hi - Z
Q0
Q3
Q2
Q1
PRE
Q0
Q3
Q2
Q1
Read
Read
T0
T1
T2
T3
T4
T5
T6
PRE
Hi - Z
In order to write all data to the memory cell correctly, the asynchronous parameter t
DPL
must be satisfied. The t
DPL
(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing t
DPL
(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS
latency
2
3
Read
-1
-2
Write
+ t
DPL
((min.)
+ t
DPL
((min.)
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IC42S16160-7TIG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16Bit x 4 Banks (256-MBIT) SDRAM
IC42S16160B-7TL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256-MBIT SYNCHRONOUS DRAM
IC42S16400 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-6BG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-6BIG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM