參數(shù)資料
型號(hào)： IC43R16160-5T
英文描述： 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述： 4米× 16位× 4個(gè)銀行（256兆）DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 37/56頁(yè)
文件大?。?/td> 1271K
代理商： IC43R16160-5T
parameter, but system performance (bus turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but system performance could be
degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS
going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRITE was in progress, DQS could be HIGH during this time, depending on
t
DQSS.
22. MIN (
t
RC or
t
RFC) for IDD measurements is the smallest multiple of
t
CK that meets the minimum absolute value
for the respective parameter.
t
RAS (MAX) for IDD measurements is the largest multiple of
t
CK that
meets the maximum absolute value for
t
RAS.
NOTES: (continued)
23. The refresh period 64ms. This equates to an average refresh rate of 7.8μs.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any
given device.
25. The valid data window is derived by achieving other specifications -
t
HP (
t
CK/2),
t
DQSQ, and
t
QH
(
t
QH =
t
HP -
t
QHS). The data valid window derates directly porportional with the clock duty cycle and a practical data
valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio.
26. Referenced to x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15.
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command
period (
t
RFC [MIN]) else CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device..
30. CK and CK input slew rate must be 1V/ns.
31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less
than 0.5V/ns, timing must be derated: 50ps must be added to
t
DS and
t
DH for each 100mv/ns reduction in slew rate.
If slew rate exceeds 4V/ns, functionality is uncertain.
IC4
3R16160
Integrated Circuit Solution Inc.
DDR001-0B
1
1
/
10
/
2004
37
相關(guān)PDF資料
PDF描述
IC43R16160-5TG 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-6T 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-6TG 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IC43R16160-5TG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-6T 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-6TG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-7T 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-7TG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
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