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參數(shù)資料
| 型號(hào)： | IC43R16160-5TG |
| 英文描述： | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| 中文描述： | 4米× 16位× 4個(gè)銀行（256兆）DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 38/56頁 |
| 文件大小： | 1271K |
| 代理商： | IC43R16160-5TG |
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NOTES: (continued)
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount.
34.
t
HP min is the lesser of
t
CL minimum and
t
CH minimum actually applied to the device CK and CK/ inputs,
collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
t
RAS(MIN) can be satisfied prior
to the internal precharge com-mand being issued.
36. Applies to x16. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid.
Initial JEDEC specifications suggested this to be same as
t
DQSQ.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie
within the outer bounding lines of the V-I curve of Figure B.
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be
between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage
and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-to-source voltages from 0.1V to 1.0 Volt.
32
.
VDD must not vary more than 4% if CKE is not active while any bank is active.
IC4
3R16160
38
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
相關(guān)PDF資料 |
PDF描述 |
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| IC43R16160-6T | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160-6TG | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160-7T | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160-7TG | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| ICS570 | Multiplier and Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC43R16160-6T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160-6TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160-7T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160-7TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160E-5TL | 制造商:Integrated Silicon Solution Inc 功能描述:256M, 2.5V, DDR, 16MX16, 200MHZ, 66 PIN |
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