參數(shù)資料
型號: IC43R16160-5TG
英文描述: 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述: 4米× 16位× 4個銀行(256兆)DDR SDRAM內(nèi)存
文件頁數(shù): 45/56頁
文件大?。?/td> 1271K
代理商: IC43R16160-5TG
Figure 38 - INITIALIZE AND MODE REGISTER SETS
CKE
LVCMOS LOW LEVEL
DQ
BA0, BA1
200 cycles of CLK**
Extended
Mode
Register
Set
Load
Mode
Register,
Reset DLL
(with A8 = H)
Load
Mode
Register
(with A8 = L)
tMRD
tMRD
tMRD
tRP
tRFC
tRFC
tIS
Power-up:
VDD and
CLK stable
T = 200
μ
s
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High-Z
tIH
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()()
()()
()()
DQS
High-Z
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
A0-A9, A11
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A10
ALL BANKS
DON'T CARE
CK
/CK
tCK
tCH
tCL
VTT
(system*)
tVTD
VREF
VDD
VDDQ
COMMAND
MRS
NOP
PRE
EMRS
AR
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AR
tIS
tIH
BA1=L
tIS
tIH
tIS
tIH
BA1=L
tIS
tIH
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CODE
tIS
tIH
CODE
MRS
BA1=L
CODE
CODE
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PRE
ALL BANKS
tIS
tIH
RA
RA
ACT
BA
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied.
The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command.
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CODE
CODE
IC4
3R16160
Integrated Circuit Solution Inc.
DDR001-0B
1
1
/
10
/
2004
45
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