參數(shù)資料
型號(hào): IC43R16160-6TG
英文描述: 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述: 4米× 16位× 4個(gè)銀行(256兆)DDR SDRAM內(nèi)存
文件頁數(shù): 17/56頁
文件大小: 1271K
代理商: IC43R16160-6TG
Burst Write Timing
Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the
burst cycle is latched into the device.
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
WRITE
NOP
NOP
NOP
D
0
D
1
D
2
D
3
CK, CK
Command
DQS(nom)
DQ(nom)
t
WPRES
t
WPREH
t
DQSS
t
WPST
t
QDQSH
D
0
D
1
D
2
D
3
DQS(min)
DQ(min)
t
DQSS
(min)
D
0
D
1
D
2
D
3
DQS(max)
DQ(max)
t
WPRES
(min)
t
DQSS
(max)
t
QDQSS
t
QDQSS
t
QDQSH
t
WPREH
(min)
t
WPREH
(max)
t
WPRES
(max)
IC4
3R16160
Integrated Circuit Solution Inc.
DDR001-0B
1
1
/
10
/
2004
17
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