參數資料
型號: IC43R16160-6TG
英文描述: 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述: 4米× 16位× 4個銀行(256兆)DDR SDRAM內存
文件頁數: 2/56頁
文件大小: 1271K
代理商: IC43R16160-6TG
Features
High speed data transfer rates with system frequency
up to 200 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
5
6
7
DDR400
7.5ns
6ns
5ns
200MHz
DDR333
7.5ns
6ns
-
166MHz
DDR266
7.5ns
7ns
-
143MHz
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
Package Outline
JESEC 66TSOP II
-5
-6
-7
Std.
L
0°C to 70°C
Blank
Operation
Temperature
Range
CK Cycle Time (ns)
Power
Temperature
Mark
The ICSI IC43R16160 is a four bank DDR DRAM
organized as 4 banks x 4Mbit x 16. The IC43R16160
achieves high speed data transfer rates by employing a
chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, circuits are synchronized with
the positive edge of an externally supplied clock. I/O
transactions are ocurring on both edges of DQS. Operating
the four memory banks in an interleaved fashion allows
random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless
data rate is possible depending on burst length,
CAS
latency and speed grade of the device.
Device Usage Chart
IC4
3R16160
4M Words x 16 Bits x 4 Banks (256-MBIT)
DDR SYNCHRONOUS DYNAMIC RAM
2
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
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