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參數(shù)資料
| 型號(hào)： | IC43R16160-7TG |
| 英文描述： | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| 中文描述： | 4米× 16位× 4個(gè)銀行（256兆）DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 1271K |
| 代理商： | IC43R16160-7TG |
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Burst Stop Command
The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS
high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a
burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay
(L
BST
) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a
burst Write cycle, the command will be treated as a NOP command.
Read Terminated by Burst Stop Command Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
BST
NOP
NOP
NOP
NOP
Read
D
0
D
1
CK, CK
Command
DQS
DQ
D
0
D
1
DQS
DQ
CAS Latency = 2
CAS Latency = 2.5
L
BST
L
BST
L
BST
IC4
3R16160
Integrated Circuit Solution Inc.
DDR001-0B
1
1
/
10
/
2004
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC43R16160E-5TL | 制造商:Integrated Silicon Solution Inc 功能描述:256M, 2.5V, DDR, 16MX16, 200MHZ, 66 PIN |
| IC43R32400 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-4B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-4BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-5B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
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