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參數(shù)資料
| 型號(hào)： | IC43R16160-7TG |
| 英文描述： | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| 中文描述： | 4米× 16位× 4個(gè)銀行（256兆）DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 6/56頁 |
| 文件大小： | 1271K |
| 代理商： | IC43R16160-7TG |
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Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA
0
(The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A
0
~ A
12
in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet t
MRD
spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
, addressing mode
uses A
3
, CAS latency (read latency from column address) uses A
4
~ A
6
. A
8
is used for DLL reset. A7 must
be set to low for normal MRS operation. Refer to the table for specific codes for various burst length,
addressing modes and CAS latencies.
1.
MRS can be issued only at all banks precharge state.
2.
Minimum tRP is required to issue MRS command.
Address Bus
CAS Latency
A
6
A
5
0
0
0
0
1
1
1
1
A
4
0
1
0
1
0
1
0
1
Latency
Reserve
Reserve
2
3
Reserve
Reserve
2.5
Reserve
0
0
1
1
0
0
1
1
Burst Length
A
2
A
1
A
0
Latency
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A
3
0
1
Burst Type
Sequential
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
A
8
0
1
DLL Reset
No
Yes
Mode Register Set
0
RFU : Must be set "0"
Extended Mode Register
Mode Register
DLL
I/O
A
0
0
1
DLL Enable
Enable
Disable
A
1
0
1
I/O Strength
Full
Half
BA
0
0
1
A
n
~ A
0
(Existing)MRS Cycle
Extended Funtions(EMRS)
Command
2
0
1
5
3
4
8
6
7
CK, CK
t
CK
t
MRD
Precharge
All Banks
Mode
Register Set
t
RP
*2
*1
Any
Command
BA
1
BA
0
A
3
A
2
A
1
A
0
0
CAS Latency
BT
Burst Length
RFU
DLL
MRS
MRS
A
12
to
IC4
3R16160
6
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC43R16160E-5TL | 制造商:Integrated Silicon Solution Inc 功能描述:256M, 2.5V, DDR, 16MX16, 200MHZ, 66 PIN |
| IC43R32400 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
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| IC43R32400-5B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
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