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參數(shù)資料
| 型號： | ICM105B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Color VGA CMOS Image Sensor |
| 中文描述： | 色VGA CMOS圖像傳感器 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 1202K |
| 代理商： | ICM105B |
ICM105B VGA CMOS sensor
Data Sheet V1.6, August 2002
2000, 2001,2002 IC Media Corporation & IC Media Technology Corp
web site:
http://www.ic-media.com/
web site:
http://www.ic-media.com.tw/
page
6
10/16/2002
Confidential
Figure 2. Color filter Bayer pattern
2.3 Exposure and Gain Control
The brightness of the scene may change by a great amount that renders the captured image either over-
exposed or under-exposed. To accommodate for different brightness, the user may change the exposure
time by adjusting the AD_EXPOSE_TIMEH and AD_EXPOSE_TIMEL. The exposure time is measured
in terms of the time to read out one line of data, which is equal to 64.17
μ
s (assuming the line length is 770
@ 24 MHz). If the number of lines per frame is set at 520 (the default), the exposure time can vary from 1
to 519 lines. In addition, the user can adjust bit 7 to 5 of register AD_COL_BEGINH to digitally boost the
output value by 1 to 64 times.
2.4 Timing Control
Timing control is performed by programming a 32-entry wave table. Its content is filled by external
circuitry after power up. Bits 19 to 10 are the control signals. Bits 9 to 0 are the change position.
Whenever the change position equals the column counter, a new set of signal values are applied. Please see
the Wave Table Programming section for details.
2.5 Output Format
During normal operation, the output format is 8-bit raw data that ranges from 0 to 255. It may be used for
off-chip color processing or compression. A typical configuration is to connect ICM-105B to a
USB/Compression combo chip. When operated at 30 fps, the PCLK is 12 MHz when the input main clock
is 24 MHz.
In addition to the data pins, the chip also output VSYNC, HSYNC, and PCLK. The length and polarity of
VSYNC and HSYNC can be adjusted through registers. The line and frame timing can be adjusted through
registers AD_WIDTH and AD_HEIGHT.
2.6 SIF Interface
Register programming is through SIF interface (SCL and SDA pins). The 7-bit SIF device address is 0x20
by default, but the last bit can be configured by the SIFID pin. ICM-105B can operate in either SIF master
mode or slave mode right after power up, depending on the pull-up or pull-down of the SIFMS pin. When
SIFMS is pulled low during power-up, ICM-105B’s SIF interface is operated as an SIF slave device,
waiting to be controlled by an external SIF master such as a microprocessor. When SIFMS is pulled high
during power-up, the SIF interface is first acting as an SIF master device trying to read from an external
SIF EEPROM. After that, it will fall back to behave like an SIF slave.
R
R
G
G
R
R
G
G
G
B
G
B
G
B
G
B
R
R
G
G
R
R
G
G
G
B
G
B
G
B
G
B
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICM107 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ICM107B Mega pixel Color CMOS image sensor |
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