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| 型號： | ICM320T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 Megapixel QXGA Digital Color CMOS Image Sensor |
| 中文描述： | 320萬像素QXGA的數(shù)字彩色CMOS圖像傳感器 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大小： | 1410K |
| 代理商： | ICM320T |
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IC M320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
C opyright 2005, IC Media C orporation
http://www.ic-media.com/
3/14/2005
Page
14
Table 2. SIF Registers Descriptions
(continued)
Bit Description
Default
Affected by
Latent
Register
Frame
Boundary
Update
0x01 TIMING CONTROL (LSB)
0x02
TIMING CONTROL (MSB)
Timing control
[0] Column count enable, set to 0 when filling register file, set
to 1 when normal operation
[1] HSYNC polarity
0: active low, 1: active high
The DOUT[5] pin determines the initial value
[2] VSYNC polarity
0: active low, 1: active high
The DOUT[6] pin determines the initial value
[3] Auto dark correction enable
When this bit is set, register 0x3B will decode which auto-
dark correction scheme will be used
[4] Timing select, 0: register file timing, 1: default timing
[6] Flash polarity, 0: active low, 1: active high
[7] Blank polarity, 0: active low, 1: active high
[8] IRST select, 0: from register file, 1: from
IRST_NUMBER register
[10] Capture: when in single frame mode, writing a 1 here
will start a frame capture
[11] Dead column removal mode, 0: color, 1: black-and-white
[12] Out-of-array exposure pointer control, 0: point to row
487, 1: point to row 490 (a non-existent row)
[13] Column stop, 0: sensor column counter stop at 649 when
exceeding real array, 1: sensor column counter keeps
counting.
0x03 PIXEL CONFIGURATION TABLE INDEX
[4:0] Index to the pixel configuration table register file.
0x04 PIXEL CONFIGURATION TABLE DATA (L)
0x05 PIXEL CONFIGURATION TABLE DATA (M)
0x06 PIXEL CONFIGURATION TABLE DATA (H)
Reserved.
0x07 PIXEL CONFIGURATION TABLE LENGTH
[4:0] Pixel configuration table register file length
0x08 LOAD PIXEL CONFIGURATION TABLE DATA
Writing into this register causes the pixel configuration table
data in registers 0x04-0x06 to be written into the pixel
configuration table entry that is indexed by register 0x03.
0x09 through 0x0B
Reserved
0x0C FRAME WIDTH (LSB)
0x0D FRAME WIDTH (MSB)
[10:0] Defines the frame width. The frame width must be
more than AD_COL_BEGIN+ 2068.
0x0011
N
N
0x00
N
N
0x000000
N
N
0x00
N
N
0x01
N
N
0x0000
N
N
0x0898
(2200)
Y
Y
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