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參數(shù)資料
| 型號(hào)： | ICM320T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 Megapixel QXGA Digital Color CMOS Image Sensor |
| 中文描述： | 320萬像素QXGA的數(shù)字彩色CMOS圖像傳感器 |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 1410K |
| 代理商： | ICM320T |
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IC M320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
C opyright 2005, IC Media C orporation
http://www.ic-media.com/
3/14/2005
Page
25
QXGA Full Resolution Mode Line Timing
For the default QXGA line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC signal
will be low for 64 PCLK clock cycles. After 100 PCLK clock cycles, DOUT [9:0] will output ten cycles of
dummy pixel data followed by 2048 cycles of image data and ten cycles of dummy pixel data. Another 32
cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure 9.
Figure 9. Default QXGA Line Timing for 2200 PCLKs
QXGA Full Resolution Mode Frame Timing
For the default QXGA frame timing, the timing unit for the frame is derived from one line-time unit, which
is 2200 PCLKs. Frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal will be
low for three line-time units. Sixteen line-time units from the start of the frame, DOUT [9:0] will output ten
lines of dummy pixel data, followed by 1536 lines of image data and another ten lines of dummy pixel data.
248 lines after the image pixel data, the VSYNC signal will be de-asserted again to start a new frame. See
Figure 10.
Figure 10. Default QXGA Frame Timing – Change Registers 0x4/0x15 to 0x0010 (H)
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| ICM320TGADA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.2 Megapixel QXGA Digital Color CMOS Image Sensor |
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| ICM-324-1-GT | 功能描述:IC 與器件插座 24P / .300" MACHINED PINS RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點(diǎn)數(shù)量:2011 觸點(diǎn)電鍍:Gold 安裝風(fēng)格:SMD/SMT 端接類型:Solder 插座/封裝類型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
| ICM3281GT | 制造商:ADAM-TECH 制造商全稱:Adam Technologies, Inc. 功能描述:SCREW MACHINE SOCKETS & TERMINAL STRIPS |
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