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參數(shù)資料
| 型號： | ICM320TCA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 Megapixel QXGA Digital Color CMOS Image Sensor |
| 中文描述： | 320萬像素QXGA的數(shù)字彩色CMOS圖像傳感器 |
| 文件頁數(shù)： | 26/30頁 |
| 文件大?。?/td> | 1410K |
| 代理商： | ICM320TCA |
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IC M320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
C opyright 2005, IC Media C orporation
http://www.ic-media.com/
3/14/2005
Page
26
1/4-Rate Subsampling Mode Line Timing
For the default 1/4-rate (1024x768) line timing, a line starts when the HSYNC signal is de-asserted. The
HSYNC signal will be low for 32 PCLK clock cycles. After 50 PCLK clock cycles, DOUT [9:0] will
output five cycles of dummy pixel data, followed by 1024 cycles of image data and another five cycles of
dummy pixel data. Sixteen cycles after the last dummy pixel data, the VSYNC signal will be de-asserted
again to start a new line. See Figure 11.
Figure 11. Default 1/4-Rate Line Timing for 1100 PCLKs
1/4-Rate Subsampling Mode Frame Timing
For the default 1/4-rate (1024x768)frame timing, the timing unit for the frame is derived from one line-time
unit, which is 1100 PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The VSYNC
signal will be low for three line-time units. Eight line-time units from the start of the frame, DOUT [9:0]
will output five lines of dummy pixel data, followed by 240 lines of image data and another five lines of
dummy pixel data. Two lines after the last dummy pixel data, the VSYNC signal will be de-asserted again
to start a new frame. See Figure 12.
Figure 12. Default 1/4-Rate Frame Timing – Change Registers 0x14/0x15 to 0x0010 (H)
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| ICM-328-1-GT | 功能描述:IC 與器件插座 28P / .300" MACHINED PINS RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點數(shù)量:2011 觸點電鍍:Gold 安裝風(fēng)格:SMD/SMT 端接類型:Solder 插座/封裝類型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
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