參數(shù)資料
型號: ICM7211AMLPLZ
廠商: INTERSIL CORP
元件分類: 顯示驅(qū)動器
英文描述: 4-Digit, LCD Display Driver
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PDIP40
封裝: ROHS COMPLIANT, PLASTIC, DIP-40
文件頁數(shù): 4/8頁
文件大?。?/td> 211K
代理商: ICM7211AMLPLZ
4
FN3158.7
April 17, 2006
Input Definitions
In this table, V
DD
and V
SS
are considered to be normal operating input logic levels. Actual input low and high levels are specified
under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT
DIP TERMINAL
CONDITIONS
FUNCTION
B0
27
V
DD
= Logical One
V
SS
= Logical Zero
Ones (Least Significant)
Data Input Bits
B1
28
V
DD
= Logical One
V
SS
= Logical Zero
Twos
B2
29
V
DD
= Logical One
V
SS
= Logical Zero
Fours
B3
30
V
DD
= Logical One
V
SS
= Logical Zero
Eights (Most Significant)
OSC
36
Floating or with External
Capacitor to V
DD
Oscillator Input
V
SS
Disables BP output devices, allowing segments to be synchronized to an
external signal input at the BP terminal (Pin 5).
Interface Input Configuration
INPUT
DESCRIPTION
DIP TERMINAL
CONDITIONS
FUNCTION
DA1
Digit Address
Bit 1 (LSB)
31
V
DD
= Logical One
V
SS
= Logical Zero
DA1 and DA2 serve as a 2-bit Digit Address Input
DA2, DA1 = 00 selects D4
DA2, DA1 = 01 selects D3
DA2, DA1 = 10 selects D2
DA2, DA1 = 11 selects D1
DA2
Digit Address
Bit 2 (MSB)
32
V
DD
= Logical One
V
SS
= Logical Zero
CS1
Chip Select 1
33
V
DD
= Inactive
V
SS
= Active
When both CS1 and CS2 are taken low, the data at the Data and Digit
Select code inputs are written into the input latches. On the rising edge
of either Chip Select, the data is decoded and written into the output
latches.
CS2
Chip Select 2
34
V
DD
= Inactive
V
SS
= Active
Timing Diagram
FIGURE 1. MICROPROCESSOR INTERFACE INPUT
CS1
(CS2)
CS2
(CS1)
DATA AND
DIGIT
ADDRESS
= DON’T CARE
t
DH
t
DS
t
WI
t
ICS
ICM7211AM
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