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9-24
Table of Features
TYPE NUMBER
OUTPUT CODE
ANNUNCIATOR LOCATIONS
INPUT
OUTPUT
ICM7231BF
Code B
Both Annunciators on BP3
Parallel Entry, 4-bit Data, 2-bit
Annunciators, 3-bit Address
8 Digits plus
16 Annunciators
ICM7232AF
Hexadecimal
Both Annunciators on BP3
Serial Entry, 4-bit Data, 2-bit
Annunciators, 4-bit Address
10 Digits plus
20 Annunciators
ICM7232BF
Code B
ICM7232CR
Code B
1 Annunciator BP1
1 Annunciator BP3
Terminal Definitions
TERMINAL
PIN NO.
DESCRIPTION
FUNCTION
ICM7231 PARALLEL INPUT NUMERIC DISPLAY
AN1
30
Annunciator 1 Control Bit
High = ON
AN2
31
Annunciator 2 Control Bit
Low = OFF
See Table 3
BD0
32
Least Significant
4-bit Binary
Data Inputs
Input
Data
(See Table 1)
HIGH = Logical One (1)
LOW = Logical Zero (0)
BD1
33
BD2
34
BD3
35
Most Significant
A0
37
Least Significant
3-bit Digit
Address Inputs
Input
Address
(See Table 2)
A1
38
A2
39
Most Significant
CS
1
Data Input Strobe/Chip Select (Note 2)
Trailing (Positive going) edge latches data, causes data input to be
decoded and sent out to addressed digit
ICM7232 SERIAL DATA AND ADDRESS INPUT
Data Input
38
Data+ Address Shift Register Input
HIGH = Logical One (1)
LOW = Logical Zero (O)
WRITE Input
39
Decode, Output, and Reset Strobe
When DATA ACCEPTED Output is LOW, positive going edge of WRITE
causes data in shift register to be decoded and sent to addressed digit,
then shift register and control logic to be reset. When DATA ACCEPTED
Output is HIGH, positive going edge of WRITE triggers reset only.
Data Clock
Input
1
Data Shift Register and Control Logic
Clock
Positive going edge advances data in shift register. ICM7232: Elev-
enth edge resets shift register and control logic.
DATA
ACCEPTED
Output
37
Handshake Output
Output LOW when correct number of bits entered into shift register.
ALL DEVICES
Display
Voltage
V
DlSP
Common
Line Driver
Outputs
2
Negative end of on-chip resistor string
used to generate intermediate voltage
levels for display. Shutdown Input.
Display voltage control. When open (or less than 1V from V
DD
) chip
is shutdown; oscillator stops, all display pins to V
DD
.
3, 4, 5
Drive display commons, or rows
Segment
Line Driver
Outputs
6 - 29
6 - 35
(On ICM7231)
(On ICM7232)
Drive display segments, or columns.
V
DD
V
SS
NOTES:
1. For Design reference only, not 100% tested.
2. CS has a special “mid-level” sense circuit that establishes a test mode if it is held near 3V for several ms. Inadvertent triggering of this
mode can be avoided by pulling it high when inactive, or ensuring frequent activity.
40
Chip Positive Supply
36
Chip Negative Supply
ICM7231, ICM7232