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參數(shù)資料
| 型號： | ICM7323Q |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DAC |
| 英文描述： | QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 8 us SETTLING TIME, 8-BIT DAC, PDSO16 |
| 封裝： | QSOP-16 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 145K |
| 代理商： | ICM7323Q |
ICM7363/7343/7323
Q
UAD
12/10/8-
BIT
V
OLTAGE
-O
UTPUT
DAC
S
APPLICATIONS INFORMATION
Power Supply Bypassing and Layout Considerations
As in any precision circuit, careful consideration has to be
given to layout of the supply and ground. The return path
from the GND to the supply ground should be short with
low impedance. Using a ground plane would be ideal. The
supply should have some bypassing on it. A 10
μ
F
tantalum capacitor in parallel with a 0.1
μ
F ceramic with a
low ESR can be used. Ideally these would be placed as
close as possible to the device. Avoid crossing digital and
analog signals, specially the reference, or running them
close to each other.
Output Swing Limitations
The ideal rail-to-rail DAC would swing from GND to V
DD
however, offset and gain error limit this ability. Figure 5
illustrates how a negative offset error will affect the output.
The output will limit close to ground since this is single
supply part, resulting in a deadband area. As a larger input
is loaded into the DAC the output will eventually rise above
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
8
IC MICROSYSTEMS
IC
mic
ground. This is why the linearity is specified for a starting
code greater than zero.
Figure 6 illustrates how a gain error or positive offset error
will affect the output when it is close to V
DD
. A positive gain
error or positive offset will cause the output to be limited to
the positive supply voltage resulting in a deadband of
codes close to full-scale. This can be avoided by using a
reference voltage slightly less then 0.5 x V
DD
ensuring that
the full-scale of the DAC is always less than V
DD
.
NEGATIVE
OFFSET
DEADBAND
Figure 5
: Effect of Negative Offset
DEADBAND
POSITIVE
OFFSET
OFFSET AND
GAIN ERROR
V
DD
Figure 6:
Effect of Gain Error and Positive Offset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICM7323QG | QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS |
| ICM7343 | QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS |
| ICM7343Q | QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS |
| ICM7343QG | QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS |
| ICM7363 | QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICM7323QG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS |
| ICM7332 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:DUAL 12/10/8-BIT VOLTAGE-OUTPUT DACS with Serial Interface and Adjustable Output Offset |
| ICM7332Q | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:DUAL 12/10/8-BIT VOLTAGE-OUTPUT DACS with Serial Interface and Adjustable Output Offset |
| ICM7332QG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:DUAL 12/10/8-BIT VOLTAGE-OUTPUT DACS with Serial Interface and Adjustable Output Offset |
| ICM7333 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain |
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