參數(shù)資料
型號： ICM7543MG
廠商： IC MICROSYSTEMS SDN BHD
元件分類： DAC
英文描述： 12/10/8-Bit Low Power Quad DACs With Serial Interface and Voltage Output
中文描述： QUAD, SERIAL INPUT LOADING, 8 us SETTLING TIME, 10-BIT DAC, PDSO10
封裝： ROHS COMPLIANT, MSOP-10
文件頁數(shù)： 6/11頁
文件大小： 205K
代理商： ICM7543MG
ICM7563/7543/7523
Rev. A7 ICmic reserves the right to change specifications without prior notice
6
C3 C2 C1 C0
DATA
(D11~D0)
(D9~D0)
(D7~D0
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
X
DAC
FUNCTION
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
B
C
D
A
B
C
D
A
B
C
D
All
All
All
All
Input Register transparent, data shifted to DAC register directly, VOA updated
Input Register transparent, data shifted to DAC register directly, VOB updated
Input Register transparent, data shifted to DAC register directly, VOC updated
Input Register transparent, data shifted to DAC register directly, VOD updated
Data Shifted to Input Register, VOA unchanged
Data Shifted to Input Register, VOB unchanged
Data Shifted to Input Register, VOC unchanged
Data Shifted to Input Register, VOD unchanged
Data Shifted from Input Register to DAC register, VOA updated
Data Shifted from Input Register to DAC register, VOB updated
Data Shifted from Input Register to DAC register, VOC updated
Data Shifted from Input Register to DAC register, VOD updated
Input Registers transparent, data shifted to DAC register directly, All OUT updated
Data Shifted to Input Registers, All VOUT unchanged
Data Shifted from Input Registers to DAC registers, All VOUT updated
Please see Power Down Mode Control Table
Table 1. Serial Interface Input Word
CONTROL
DATA
DAC
FUNCTION
C3 C2 C1 C0
D11~D5
D9~D3
D7~D1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D4
D2
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
D3
D1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
D2
D0
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0 (7563)
A0 (7543)
A0 (7523)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
All
All
All
All
DAC O/P, wakeup
Floating Output
Output is terminated
with 1K
Output is terminated with100 K
DAC O/P, wakeup
Floating Output
Output is terminated with 1K
Output is terminated with100 K
DAC O/P, wakeup
Floating Output
Output is terminated with 1K
Output is terminated with100 K
DAC O/P, wakeup
Floating Output
Output is terminated with 1K
Output is terminated with100 K
DAC O/P, wakeup
Floating Output
Output is terminated with 1K
Output is terminated with100 K
Table 2. Power Down Mode Control
相關(guān)PDF資料
PDF描述
ICM7563 12/10/8-Bit Low Power Quad DACs With Serial Interface and Voltage Output
ICM7563M 12/10/8-Bit Low Power Quad DACs With Serial Interface and Voltage Output
ICM7563MG 12/10/8-Bit Low Power Quad DACs With Serial Interface and Voltage Output
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